Pixelated displays use image data to control the display state of each pixel. Before being sent to individual pixels, this data may be stored in a memory store of a slave display module after being sent from a master display controller. The memory store may be mounted on a substrate of the module along with the pixel matrix and associated circuitry.
To refresh the image displayed, it is common for the memory store to hold data indicative of the display state of each pixel. However, with the miniaturisation of pixel technology and the associated increase of the number of pixels in a display, the physical size of the memory store required increases accordingly. For example, for a video graphics display (VGA) of 480 rows and 640 columns of pixels, with a pixel refresh rate of 60 Hz, a 440 Mbits/s speed memory store is required. A memory store of this speed has a significant power consumption, which is problematic for mobile devices powered by batteries. Moreover, such a memory store is bulky and thus occupies a large area of the substrate. This is problematic since a substrate, for example of silicon, with the required area is expensive and would enlarge the size of the display.
The size of the memory store can be reduced by refreshing the pixel display states on a row by row basis, rather than frame by frame. Accordingly, the memory store can be linear, storing pixel data of one row of pixels at a time; see for example US patent publication no. 2007/0063954. A problem with this approach is that the data stored by the memory needs to be refreshed more often; for example, a memory store of 640 bits in length for the above-mentioned VGA display would need to be refreshed at a rate of 480×60 Hz. Such a refresh rate is very high and difficult to achieve. Further, a higher refresh rate involves greater power consumption, again causing problems for mobile applications. Moreover, a high amount of electromagnetic interference (EMI) is produced.
It is an object of the present invention to provide an improved display device.